NAND

Introduction

Octal Serial Peripheral Interface (OSPI) and Quad Serial Peripheral Interface (QSPI) are SPI modules that have x8 IO lines and x4 IO lines respectively. These controllers are mainly used to interface with Octal and Quad SPI flashes. OSPI is backward compatible with QSPI. These modules can also work in dual (x2) and single (x1) modes. OSPI and QSPI controllers on TI SoCs support memory mapped IO interface, which provide a direct interface for accessing data from the external SPI flash, thereby simplifying software requirements. These controllers work only in master mode.

Note

Not all OSPI flashes can be supported. Users are recommended to check whether or not the OSPI flash part chosen for custom board designs meets all the criteria listed at https://e2e.ti.com/support/processors/f/791/t/946418

Driver Features

OSPI controllers supports PHY Calibration in DQS + Double Data Rate (DDR) mode for OSPI/QSPI NOR flashes in Octal configuration wherein data can be read on both edges of the clock, and non-DQS + Single Data Rate (SDR) mode for OSPI/QSPI NAND flashes in Quad and Octal configuration.

Memory mapped read support

Once the controller is configured in memory map mode, the whole flash memory is made available as a memory region at an SoC specific address. This region can be accessed using normal memcpy() (or mem-to-mem dma copy). Controller hardware will internally communicate with SPI flash over SPI bus and get the requested data. This mode provides the best throughput and is the default mode in the SDK.

Supported SPI modes

The cadence_qspi.c driver supports standard SPI mode 0 only.

DMA support

The driver uses mem-to-mem DMA copy on top of an OSPI/QSPI memory mapped port during flash read operations for maximum throughput and reduced CPU load.

The OSPI Controller does not support interfacing with non-flash SPI slaves.

Driver Configuration

Source Location

OSPI driver is at: drivers/spi/cadence_qspi.c under U-Boot source tree. This driver also supports QSPI version of the same IP.

DT Configuration

Flash properties:

compatible: specifies the compatible string for the device, the operating system uses this string to identify and the match the driver for the device. Use ‘jedec,spi-nor’ for OSPI/QSPI NOR flashes and ‘spi-nand’ for OSPI/QSPI NAND flashes.
spi-tx-bus-width and spi-rx-bus-width: specifies the bus width in bits for SPI transactions when transmitting (tx) and receiving (rx) data. Set for ‘8’ for OSPI flashes and ‘4’ for QSPI flashes.
spi-max-frequency: defines the maximum frequency in Hertz at which the SPI bus can operate. Set 1/4th or 1/8th of ‘assigned-clocks’ value of ‘ospi0’ node for SDR and DDR mode respectively. If PHY Calibration is enabled, this value is ignored, and the maximum frequency is determined by the value specified in the ‘assigned-clocks’ property of ‘ospi0’ node.
cdns,read-delay: specifies the delay in clock cycles between the fetch of a command and responding to that command by the flash devices. This differs with flashes, try with different read delays starting from 0 and find the minimum read-delay at which the flash driver probes correctly.

Note

The sf command is used to access SPI NOR flash, supporting read/write/erase and a few other functions. For more information on sf command in U-boot please refer to the u-boot documentation: here. And for accessing SPI NAND flash, the mtd command is used, supporting read/write/erase and bad block management.